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document number: mma51xxkw rev. 9, 03/2012 freescale semiconductor data sheet: technical data ? 2010-2012 freescale semiconducto r, inc. all ri ghts reserved. psi5 inertial sensor the mma51xxkw family, a safeassure solution, includes the aklv27 and psi5 version 1.3 compatible overdamped z-axis satellite accelerometers. features ? 60g to 480g full-scale range ? selectable 400 hz, 3-pole, or 4-pole low-pass filter ? single pole high pass filter with fast startup and output rate limiting ? psi5 version 1.3 compatible ? psi5-p10p-500/3l compatible ? programmable time slots with 0.5 s resolution ? selectable baud rate: 125 kbaud or 190.5 kbaud ? selectable data length: 8 or 10 bits ? selectable error detection: even parity, or 3-bit crc ? optional daisy chain with external low side switch ? two-wire programming mode ? 16 s internal sample rate, with interpolation to 1 s ? pb-free 16-pin qfn, 6 by 6 package ? qualified aecq100, revision g, grade 1 (-40 c to +125 c) ( http://www.aecouncil.com/ ) typical applications ? airbag front and side crash detection for user register array programming, please consult your freescale representative. ordering information device axis range package shipping mma5106kw z 60g 2086-01 tubes mma5112kw z 120g 2086-01 tubes MMA5124KW z 240g 2086-01 tubes mma5148kw z 480g 2086-01 tubes mma5106kwr2 z 60g 2086-01 tape & reel mma5112kwr2 z 120g 2086-01 tape & reel MMA5124KWr2 z 240g 2086-01 tape & reel mma5148kwr2 z 480g 2086-01 tape & reel mma51xxkw 16-pin qfn case 2086-01 pin connections bottom view top view v cc v ss bus_sw v ssa test v buf d out d in v rega cs v reg v ss i data slck v ssa pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17
sensors 2 freescale semiconductor, inc. mma51xxkw application diagram figure 1. application diagram device orientation figure 2. device orientation diagram external component recommendations ref des type description purpose c1 ceramic 2.2 nf, 10%, 50v minimum, x7r v cc power supply decoupling and signal damping c3 ceramic 470 pf, 10%, 50v minimum, x7r i data filtering and signal damping c2 ceramic 15 nf, 10%, 50v minimum, x7r v cc power supply decoupling c4, c5, c6 ceramic 1 f, 10%, 10v minimum, x7r voltage regulator output capacitor(s) r1 general purpose 82, 5%, 200 ppm v cc filtering and signal damping r2 general purpose 27 , 5%, 200 ppm i data filtering and signal damping r3 general purpose 20 k , 5%, 200 ppm gate resistor for external low side daisy chain fet m1 n-channel mosfet ? low side daisy chain transistor c1 c6 vv buf v ce v ss c4 c5 v reg v rega cs sclk do di mma51xx v ssa v ss v cc v buf pcm r1 r2 i data c3 c2 v ss_out r3 m1 optional for bus_sw note: pin names and references may differ from psi5 v1.3 pin names and references daisy chain z: 0g earth ground z: 0g z: 0g z: 0g z: +1g z: -1g xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx
sensors freescale semiconductor, inc. 3 mma51xxkw internal block diagram figure 3. block diagram self-test interface ? converter v cc serial encoder v buf sync pulse detection programming interface pcm v buf v ss buffer regulator voltage digital regulator voltage analog regulator voltage v reg v rega v rega v reg v cc v reg v rega v reg reference voltage v ref v ssa d in spi d out cs sclk i data v buf daisy chain switch driver bus_sw control logic otp array g-cell control in status out sinc filter compensation lpf iir pcm dsp hpf low voltage detection encoder offset monitor
sensors 4 freescale semiconductor, inc. mma51xxkw 1 pin connections figure 4. top view, 16-pin qfn package table 1. pin description pin pin name formal name definition 1 v cc supply this pin is connected to the psi5 power and data line through a resistor and supplies power to the device. an external capac- itor must be connected between this pin and v ss . reference figure 1 . 2 v ss digital gnd this pin is the power supply return node for the digital circuitry. 3 i data response current this pin is connected to the psi5 power and data line through a resistor and modulates the response current for psi5 com- munication. reference figure 1 . 4 v ss digital gnd this pin is the power supply return node for the digital circuitry. 5 pcm pcm output this pin provides a 4 mhz pcm signal proportional to the acce leration data for test purposes. the output can be enabled via otp. reference section 3.5.3.7 . if unused, this pin must be left unconnected. 6 sclk spi clock this input pin provides the serial clock to the spi port for test purposes. an internal pulldown device is connected to this pi n. this pin must be grounded or left unconnected in the application. 7 d out spi data out this pin functions as the serial data output from the spi port for test purposes. this pin must be left unconnected in the appl i- cation. 8 d in spi data in this pin functions as the serial data input to the spi port fo r test purposes. an internal pu lldown device is connected to this pin. this pin must be grounded or left unconnected in the application. 9 v reg digital supply this pin is connected to the power supply for the internal digital circuitry. an external capacitor must be connected between this pin and v ss . reference figure 1 . 10 cs chip select this input pin provides the chip select to the spi port for test purposes. an internal pullup device is connected to this pin.t his pin must be left unconnected in the application. 11 v rega analog supply this pin is connected to the power supply for the internal analog circuitry. an external capacitor must be connected between this pin and v ssa . reference figure 1 . 12 vssa analog gnd this pin is the power supply return node for the analog circuitry. 13 v buf power supply this pin is connected to a buffer regulator for the internal circuitry. the buffer regulator supplies both the analog (v rega ) and digital (v reg ) supplies to provide immunity from emc and supply dropouts on v cc . an external capacitor must be connected between this pin and v ss . reference figure 1 . 14 test test pin this pin is must be grounded or left unconnected in the application. 15 bus_sw bus switch gate drive this pin is the drive for a low side daisy chain switch. when da isy chain mode is enabled, this pin is connected to the gate of an n-channel fet which connects v ss to v ss_out. reference figure 1 . if unused, this pin must be left unconnected. 16 vssa analog gnd this pin is the power supply return node for the analog circuitry. 17 pad die attach pad this pin is the die attach flag, and is internally connected to vss. reference section 6 for die attach pad connection details. corner pads corner pads the corner pads are internally connected to v ss . v cc v ss bus_sw v ssa test v buf d out d in v rega cs v reg v ss i data slck v ssa pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17
sensors freescale semiconductor, inc. 5 mma51xxkw 2 electrical characteristics 2.1 maximum ratings maximum ratings are the extreme limits to which the dev ice can be exposed without permanently damaging it. 2.2 operating range v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # rating symbol value unit 1 2 3 supply voltage (v cc , i data ) reverse current 160 ma, t 80 ms continuous transient (< 10 s) v cc_rev v cc_max v cc_trans -0.7 +20.0 +25.0 v v v (3) (3) (9) 4 v buf, test, bus_sw -0.3 to +4.2 v (3) 5 v reg , v rega , sclk, cs , d in , d out , pcm -0.3 to +3.0 v (3) 6 powered shock (six sides, 0.5 ms duration) g pms 2000 g (3) 7 unpowered shock (six sides, 0.5 ms duration) g shock 2500 g (3) 8 drop shock (to concrete, tile or steel surface, 10 drops, any orientation) h drop 1.2 m (5) 9 10 11 12 electrostatic discharge (per aec-q100) external pins (v cc , i data , v ss , v ssa ), hbm (100 pf, 1.5 k ) hbm (100 pf, 1.5 k ) cdm (r = 0 ) mm (200 pf, 0 ) v esd v esd v esd v esd 4000 2000 1500 200 v v v v (5) (5) (5) (5) 13 14 temperature range storage junction t stg t j -40 to +125 -40 to +150 c c (3) (9) 15 thermal resistance jc 2.5 c/w (9,14) # characteristic symbol min typ max units 16 17 supply voltage v cc v cc_uv v l 4.2 v vcc_uv_f ? ? v h 17.0 v l v v (1) (9) 18 programming voltage (i data 85 ma) applied to i data, v cc v pp 14.0 ? ? v (3) 19 20 operating temperature range t a t a t l -40 -40 ? ? t h +105 +125 c c (1) (3)
sensors 6 freescale semiconductor, inc. mma51xxkw 2.3 electrical characteristics - supply and i/o v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 21 quiescent supply current * i idle 4.0 ? 8.0 ma (1) 22 modulation supply current * i mod i idle + 22.0 i idle + 26.0 i idle + 30.0 ma (1) 23 inrush current (power on until v buf , v reg , v rega stable) i inrush ?? 30 ma (3) 24 25 26 internally regulated voltages v buf v reg v rega * * * v buf v reg v rega 3.60 2.425 2.425 3.80 2.50 2.50 4.00 2.575 2.575 v v v (1) (1) (1) 27 28 29 30 31 32 33 34 low voltage detection threshold v cc falling v buf falling v reg falling v rega falling hysteresis v cc v buf v reg v rega v vcc_uv_f v buf_uv_f v reg_uv_f v rega_uv_f v cc_hyst v buf_hyst v reg_hyst v rega_hyst 3.40 2.95 2.15 2.15 0.10 0.05 0.05 0.05 3.70 3.15 2.25 2.25 0.25 0.10 0.10 0.10 4.0 3.35 2.35 2.35 0.40 0.15 0.15 0.15 v v v v v v v v (3, 6) (3, 6) (3, 6) (3, 6) (3) (3) (3) (3) 35 36 external capacitor (v buf , v reg , v rega ) capacitance esr (including interconnect resistance) esr 500 0 1000 ? 1500 200 nf m (9) (9) 37 38 synchronization pulse (see figure 5 ) v idle voltage range dc sync pulse detection threshold * * v idle v sync ? v idle +1.4 ? v idle +2.0 15.4 v idle +2.6 v v (3, 11) (3, 6) 39 sync pulse pulldown current i sync_pd ? i mod - i idle ? ma (3) 40 output high voltage (do) i load = 100 av oh v reg - 0.1 ?? v(9) 41 output low voltage (do) i load = 100 av ol ?? 0.1 v (9) 42 input high voltage cs , sclk, di v ih 0.7 * v reg ?? v(9) 43 input low voltage cs , sclk, di v il ?? 0.3 * v reg v(9) 44 45 input current high (at v ih ) (di) low (at v il ) (cs ) i ih i il -100 10 ? ? -10 100 a a (9) (9) 46 pulldown resistance (sclk) r pd 20 ? 100 k (9) 47 48 temperature monitoring under-temperature monitor threshold over-temperature monitor threshold t ih t il ? 155 ? ? -55 ? c c (9) (9) 49 bus_sw output high voltage (bus_sw) i load = 100 av bus_sw_oh 3.15 ? v buf v(9) 50 output low voltage (bus_sw) i load = 100 av bus_sw_ol 0.0 ? 0.45 v (9) 51 daisy chain addressing mode sync pulse period ? t s-s_pm_l ? s(7) 52 bus switch output activation time (c = 50 pf) from last bit of ?setadr? response to 80% of v bus_sw_oh t bus_sw ?? 300 s(7) 53 sync pulse blanking time after ?setadr? command received from last bit of ?setadr? response t dc_blanking 200000 / f osc s(7)
sensors freescale semiconductor, inc. 7 mma51xxkw 2.4 electrical characteristi cs - sensor and signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. 2.5 electrical characteristics - self-test and overload v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 54 55 56 57 58 59 60 61 62 63 sensitivity (10-bit output @ 100 hz, referenced to 0 hz) 60g range 120g range 240g range 480g range total sensitivity error (including non-linearity) t a = 25 c, 240g t l t a t h , 240g t l t a t h , 240g, v vcc_uv_f v cc v l t a = 25 c, > 240g t l t a t h , > 240g t l t a t h , > 240g, v vcc_uv_f v cc v l * * * * * * * * sens sens sens sens sens_240 sens_240 sens_240 sens_480 sens_480 sens_480 ? ? ? ? -5 -7 -7 -5 -7 -7 8 4 2 1 ? ? ? ? ? ? ? ? ? ? +5 +7 +7 +5 +7 +7 lsb/g lsb/g lsb/g lsb/g % % % % % % (1) (1) (1) (1) (1) (1) (9) (1) (1) (9) 64 65 digital offset before offset cancellation 10-bit 10-bit, t l t a t h , v vcc_uv_f v cc v l * off 10bit off 10bit -52 -52 0 0 +52 +52 lsb lsb (1) (9) 66 67 digital offset after offset cancellation 10-bit, 0.3 hz hpf or 0.1 hz hpf 10-bit, 0.04 hz hpf * * off 10bit off 10bit -1 -2 0 0 +1 +2 lsb lsb (1) (9) 68 continuous offset monitor limit 10-bit output, before compensation off mon -66 ? +66 lsb (3) 69 range of output (10-bit mode) acceleration range -480 ? +480 lsb (3) 70 71 cross-axis sensitivity x-axis to z-axis y-axis to z-axis * * v xz v yz -5 -5 ? ? +5 +5 % % (3) (3) 72 system output noise peak (10-bit mode, 1 hz - 1 khz, all ranges) * n peak -4 ? +4 lsb (3) 73 system output noise rms (10-bit mode, 1 hz - 1 khz, all ranges) * n rms ??+ 1 . 0l s b( 3 ) 74 75 non-linearity 10-bit output , 240g 10-bit output, > 240g nl out_240g nl out_480g -2 -2 ? ? +2 +2 % % (3) (3) # characteristic symbol min typ max units 76 77 78 79 10-bit output during active self-test (t l t a t h ) 60g range 120g range 240g range 480g range * * * * g st10_60z g st10_120z g st10_240z g st10_480z 120 40 35 12 ? ? ? ? 280 160 153 94 lsb lsb lsb lsb (3) (3) (3) (3) 80 81 acceleration (without hitting internal g-cell stops) 60g range positive 60g range negative g g-cell_clip60zp g g-cell_clip60zn 425 -1205 642 -720 980 -512 g g (9) (9) 82 83 acceleration (without hitting internal g-cell stops) 120g range positive 120g range negative g g-cell_clip120zp g g-cell_clip120zn 425 -1205 642 -720 980 -512 g g (9) (9) 84 85 acceleration (without hitting internal g-cell stops) 240g range positive 240g range negative g g-cell_clip240zp g g-cell_clip240zn 1450 -3100 2180 -2210 2800 -1800 g g (9) (9) 86 87 acceleration (without hitting internal g-cell stops) 480g range positive 480g range negative g g-cell_clip480zp g g-cell_clip480zn 2200 -3700 2800 -3220 3300 -2780 g g (9) (9) 88 89 ? and sinc filter clipping limit 60g range positive 60g range negative g adc_clip60zp g adc_clip60zn 159 -334 238 -274 336 -216 g g (9) (9) 90 91 ? and sinc filter clipping limit 120g range positive 120g range negative g adc_clip120zp g adc_clip120zn 305 -693 433 -544 577 -414 g g (9) (9) 92 93 ? and sinc filter clipping limit 240g range positive 240g range negative g adc_clip240zp g adc_clip240zn 836 -1909 1178 -1566 1599 -1245 g g (9) (9) 94 95 ? and sinc filter clipping limit 480g range positive 480gz range negative g adc_clip480zp g adc_clip480zn 1591 -3217 2014 -2856 2478 -2524 g g (9) (9)
sensors 8 freescale semiconductor, inc. mma51xxkw 2.6 dynamic electrical characteristics - psi5 v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified # characteristic symbol min typ max units 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 initialization timing phase 1 phase 2 (10-bit, synchronous mode, k = 4) phase 2 (8-bit, synchronous mode, k = 8) phase 2 (10-bit, asynchronous mode 0, k = 8) phase 2 (8-bit, asynchronous mode 0, k = 16) phase 3 (10-bit, synchr onous mode, st_rpt = 0) phase 3 (8-bit, synchronous mode, st_rpt = 0) phase 3 (10-bit, asynchrono us mode 0, st_rpt = 0) phase 3 (8-bit, asynchronous mode 0, st_rpt = 0) offset cancellation stage 1 operating time offset cancellation stage 2 operating time self-test stage 1 operating time self-test stage 2 operating time self-test stage 3 operating time self-test repetitions programming mode entry window t psi5_init1 t psi5_init2_10s t psi5_init2_8s t psi5_init2_10a0 t psi5_init2_8a0 t psi5_init3_10s t psi5_init3_8s t psi5_init3_10a0 t psi5_init3_8a0 t oc1 t oc2 t st1 t st2 t st3 st_rpt t pme ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? 532000 / f osc 256 * t s-s 288 * t s-s 512 * t async 576 * t async 2 * t s-s 2 * t s-s 19 * t async 2 * t async 320000 / f osc 280000 / f osc 128000 / f osc 128000 / f osc 128000 / f osc ? 300000 / f osc ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5 ? s s s s s s s s s s s s s s s (7) (7) (7) (7) (7) (7, 12) (7, 12) (7, 12) (7, 12) (7) (7) (7) (7) (7) (7, 12) (7) 112 113 114 115 116 117 118 119 120 121 122 123 synchronization pulse ( figure 5 , figure 28 and figure 32 ) reset to first sync pulse (program mode entry) reset to first sync pulse (normal mode) sync pulse period sync pulse width sync pulse reference lpf time constant sync pulse reference discharge start time sync pulse reference di scharge activation time sync pulse detection disable time (blanktime = 0) analog delay of sync pulse detection sync pulse pulldown function delay time sync pulse pulldown function activate time sync pulse detection jitter t rs_pm t rs t s-s t sync t sync_lpf t sync_lpf_rst_st t sync_lpf_rst t sync_off_500 t a_sync_dly t pd_dly t pd_on t sync_jit 58 t psi5_init1 t sync_off 9 120 ? ? ? 50 ? ? 0 ? ? ? ? 280 66 / f osc 616 / f osc 1810 / f osc ? 74 / f osc 64 / f osc ? ? ? ? ? ? ? ? ? 600 ? ? 2 / f osc ms s s s s s s s ns s s s (7) (7) (7) (7) (9) (7) (7) (7) (9) (7) (7) (7) 124 125 data transmission single bit time (psi5 low bit rate) data transmission single bit time (psi5 high bit rate) * * t bit_low t bit_hi 7.6000 4.9875 8.0000 5.2500 8.4000 5.5125 s s (7) (7) 126 127 modulation current (20% to 80% of i mod - i idle ) rise time fall time t rise t fall 324 324 463 463 602 602 ns ns (3) (3) 128 129 position of bit transition (psi5 low baud rate) position of bit transition (psi5 high baud rate) * * t bittrans_lowbaud t bittrans_highbaud 49 47 50 ? 51 53 % % (7) (7) 130 asynchronous response time * t async ? 912 / f osc ? s(7) 131 132 133 134 135 136 137 138 time slots minimum programmed time slot (timeslotx = 0x001) maximum programmed time slot (timeslotx = 0x3ff) default time slot (timeslotx = 0x000) time plot resolution sync pulse to daisy chain default time slot 1 sync pulse to daisy chain default time slot 2 sync pulse to daisy chain default time slot 3 sync pulse to daisy chain programming time slot * t timeslotx_min t timeslotx_max t timeslot_dflt t timeslotx_res t timeslot_dc1 t timeslot_dc2 t timeslot_dc3 t timeslot_dcp ? ? ? ? ? ? ? ? 2 / f osc 2046 / f osc 186 / f osc 2 / f osc 186 / f osc 768 / f osc 1400 / f osc 186 / f osc ? ? ? ? ? ? ? ? s s s s/lsb s s s s (7, 9) (3, 7) (3, 7) (7) (7) (7) (7) (7) 139 140 data interpolation latency ( figure 35 , figure 36 ) data setup time - synchronous mode ( figure 36 ) data setup time - double sample rate mode ( figure 37 ) data setup time - 16 bit resolution mode ( figure 39 ) t lat_interp t datasetup_synch t datasetup_double t datasetup_16 64 / f osc 48 / f osc 48 / f osc 48 / f osc ? ? ? ? 65 / f osc 56 / f osc 60 / f osc 60 / f osc s s s s (7) (7) (7) (7) 141 142 143 144 145 programming mode timing programming mode sync pulse period programming mode command timeout otp write command to v cc = v pp otp write cmd response to otp programming start time to program one otp bit t s-s_pm_l t pm_timeout t prog_hold t prog_delay t prog_bit 495 ? ? ? 512 500 4 * t s-s_pm ? ? ? 505 ? 20 40 ? s s s ms s (7) (7) (7) (7) (7)
sensors freescale semiconductor, inc. 9 mma51xxkw 2.7 dynamic electrical char acteristics - signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified # characteristic symbol min typ max units 146 internal oscillator frequency * f osc 3.80 4 4.20 mhz (1) 147 148 149 150 dsp low-pass filter (note15) cutoff frequency lpf0 (referenced to 0 hz) filter order lpf0 cutoff frequency lpf1 (referenced to 0 hz) filter order lpf1 * * * * f c_lpf0 o lpf0 f c_lpf1 o lpf1 ? ? ? ? 400 3 400 4 ? ? ? ? hz 1 hz 1 (7) (7) (7) (7) 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 dsp offset cancellation low-pass filter (note15) offset cancellation low-pass filter input sample rate stage 1 cutoff frequency, startup phase 1 stage 1 filter order, startup phase 1 stage 2 cutoff frequency, startup phase 1 stage 2 filter order, startup phase 1 cutoff frequency, option 0 filter order, option 0 cutoff frequency, option 1 filter order, option 1 cutoff frequency, option 2 filter order, option 2 offset cancellation output update rate (8-bit mode) offset cancellation output step size (8-bit mode) offset cancellation output update rate (10-bit mode) offset cancellation output step size (10-bit mode) offset monitor update frequency offset monitor count limit offset monitor counter size t oc_samplerate f c_oc10 o oc10 f c_oc03 o oc03 f c_oc0 o oc0 f c_oc1 o oc1 f c_oc2 o oc2 t offrate_8 off step_8 t offrate_10 off step_10 offmon osc offmon cntlimit offmon cntsize ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 256 10.0 1 0.300 1 0.100 1 0.040 1 f osc / 2e6 0.125 f osc / 2e6 0.5 f osc / 2000 4096 8192 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s hz 1 hz 1 hz 1 hz 1 s lsb s lsb hz 1 1 (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) 167 168 169 170 sensing element natural frequency 60g 120g 240g 480g f gcell_z60 f gcell_z120 f gcell_z240 f gcell_z480 7000 7000 13600 16289 ? ? ? ? 8000 8000 15100 17996 hz hz hz hz (9) (9) (9) (9) 171 172 173 174 sensing element roll-off frequency (-3 db) 60g 120g 240g 480g f gcell_z60 f gcell_z120 f gcell_z240 f gcell_z480 798 798 2000 2250 ? ? ? ? 2211 2211 4700 6350 hz hz hz hz (9) (9) (9) (9) 175 176 177 178 sensing element damping ratio 60g 120g 240g 480g gcell_z60 gcell_z120 gcell_z240 gcell_z480 1.870 1.870 1.750 1.250 ? ? ? ? 4.610 4.610 3.500 3.000 ? ? ? ? (9) (9) (9) (9) 179 180 181 182 sensing element delay (@100 hz) 60g 120g 240g 480g f gcell_delay_z60 f gcell_delay_z120 f gcell_delay_z240 f gcell_delay_z480 77 77 40 21 ? ? ? ? 200 200 86 60 s s s s (9) (9) (9) (9) 183 package resonance frequency f package 100 ?? khz (9)
sensors 10 freescale semiconductor, inc. mma51xxkw 2.8 dynamic electrical char acteristics - supply and spi v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified 1. parameters tested 100% at final test. 2. parameters tested 100% at wafer probe. 3. verified by characterization. 4. * indicates critical characteristic. 5. verified by qualification testing. 6. parameters verified by pass/fail testing in production. 7. functionality guaranteed by modeling, simulation and/or desi gn verification. circuit integrity assured through iddq and scan testing. timing is determined by inter nal system clock frequency. 8. n/a. 9. verified by simulation. 10. n/a. 11. measured at v cc pin; v sync guaranteed across full v idle range. 12. self-test repeats on failure up to a st_rpt max times before transmitting sensor error message. 13. n/a. 14. thermal resistance between the die junction and the ex posed pad; cold plate is attached to the exposed pad. 15. filter cutoff frequencies are directly d ependent upon the internal oscillator frequency. # characteristic symbol min typ max units 184 quiescent current settling time (power applied to iq = i idle 2 ma) t set ?? 5ms(3) 185 reset recovery internal delay (after internal por) t int_init ? 16000 / f osc ? s(7) 186 187 188 v cc micro-cut (c buf =c reg =c rega =1 f) survival time (v cc disconnect without reset, c buf =c reg =c rega =700 nf) survival time (v cc disconnect without reset, c buf =c reg =c rega =1 f) reset time (v cc disconnect above which reset is guaranteed) t vcc_microcutmin t vcc_microcut t vcc_reset 30 50 ? ? ? ? ? ? 1000 s s s (3) (3) (3) 189 190 191 192 v buf , capacitor monitor disconnect time ( figure 10 ) por to first capacitor test disconnect disconnect time ( figure 10 ) disconnect delay, asynchronous mode ( figure 10 ) disconnect delay, synchronous mode ( figure 11 ) t por_captest t captest_time t captest_adly t captest_sdly ? ? ? 12000 / f osc 6 / f osc 688 / f osc 72 / f osc ? ? ? ? s s s s (7) (7) (7) (7) 193 194 195 v reg , v rega capacitor monitor por to first capacitor test disconnect disconnect time disconnect rate t por_captest t captest_time t captest_rate ? ? ? 12000 / f osc 6 / f osc 256 / f osc ? ? ? s s s (7) (7) (7) 196 197 198 199 200 201 202 203 204 205 206 207 208 209 serial interface timing (see figure 7 , c dout 80 pf, r dout 10 k ) clock (sclk) period (10% of v cc to 10% of v cc ) clock (sclk) high time (90% of v cc to 90% of v cc ) clock (sclk) low time (10% of v cc to 10% of v cc ) clock (sclk) rise time (10% of v cc to 90% of v cc ) clock (sclk) fall time (90% of v cc to 10% of v cc ) cs asserted to sclk high (cs = 10% of v cc to sclk = 10% of v cc ) cs asserted to d out valid (cs = 10% of v cc to d out = 10/90% of v cc ) data setup time (d in = 10/90% of v cc to sclk = 10% of v cc ) d in data hold time (sclk = 90% of v cc to d in = 10/90% of v cc ) d out data hold time (sclk = 90% of v cc to d out = 10/90% of v cc ) sclk low to data valid (sclk = 10% of v cc to d out = 10/90% of v cc ) sclk low to cs high (sclk = 10% of v cc to cs = 90% of v cc ) cs high to d out disable (cs = 90% of v cc to d out = hi z) cs high to cs low (cs = 90% of v cc to cs = 90% of v cc ) t sclk t sclkh t sclkl t sclkr t sclkf t lead t access t setup t hold_in t hold_out t valid t lag t disable t csn 320 120 120 ? ? 60 ? 20 10 0 ? 60 ? 1000 ? ? ? 15 15 ? ? ? ? ? ? ? ? ? ? ? ? 40 28 ? 60 ? ? ? 50 ? 60 ? ns ns ns ns ns ns ns ns ns ns ns ns ns ns (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9)
sensors freescale semiconductor, inc. 11 mma51xxkw figure 5. sync pulse characteristics figure 6. powerup timing figure 7. serial interface timing gnd v cc t sync v sync v sync t rs t s-s v idle v cc por v cc_uv_f + v cc_hyst time v reg v buf v cc_uv_f v buf_uv_f + v buf_hyst v buf_uv_f v reg_uv_f + v reg_hyst v reg_uv_f v reg v rega_uv_f +v rega_hyst v rega_uv_f response terminated if in process t sclk sclk d in cs d out t sclkh t sclkl t access t sclkr t sclkf t lead t csn t setup t hold_in t valid t disable t hold_out t lag
sensors 12 freescale semiconductor, inc. mma51xxkw 3 functional description 3.1 user accessible data array a user accessible data array allows for each device to be cu stomized. the array consists of an otp factory programmable block, an otp user programmable block, and read only regi sters for device status. the otp blocks incorporate independent crc circuitry for fault detection (reference section 3.2 ). portions of the factory programmab le array are reserv ed for factory-pro- grammed trim values. the user accessible data is shown in ta b l e 2 . type codes f: freescale programmed otp location u: user programmable otp location via psi5 r: readable register via psi5 3.1.1 device serial number registers a unique serial number is programmed into the serial number re gisters of each device during manufacturing. the serial num- ber is composed of the following information: serial numbers begin at 1 for all produced devices in each lo t and are sequentially assigned. lot numbers begin at 1 and are sequentially assigned. no lot will contain more devices than ca n be uniquely identified by the 13-bit serial number. depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. the serial number registers are included in the factory programmed otp crc verification. reference section 3.2.1 for details regarding the crc verification. beyond this, the contents of the seri al number registers have no impact on device operation or performance, and are only used for traceability purposes. table 2. user accessible data byte addr (xlong msg) register nibble addr (long msg) bit function nibble addr (long msg) bit function type 7654 3210 $00 sn0 $01 sn[7] sn[6] sn[5] sn[4] $00 sn[3] sn[2] sn[1] sn[0] f, r $01 sn1 $03 sn[15] sn[14] sn[13] sn[12] $02 sn[11] sn[10] sn[9] sn[8] $02 sn2 $05 sn[23] sn[22] sn[21] sn[20] $04 sn[19] sn[18] sn[17] sn[16] $03 sn3 $07 sn[31] sn[30] sn[29] sn[28] $06 sn[27] sn[26] sn[25] sn[24] $04 devcfg1 $ 0 90010 $08 1 rng[2] rng[1] rng[0] $05 devcfg2 $0b lock_u pcm sync_pd latency $0a datasize blanktime p_crc baud u, r $06 devcfg3 $0d trans_md[1] trans_md[0] lpf[1] lpf[0] $0c timeslotb[9] timeslotb[8] timeslota[9] timeslota[8] $07 devcfg4 $0f timeslota[7] timeslota[6] timeslota[5] timeslota[4] $0e timeslota[3] timeslota[2] timeslota[1] timeslota[0] $08 devcfg5 $11 timeslotb[7] timeslotb[6] timeslotb[5] timeslotb[4] $10 timeslotb[3] timeslotb[2] timeslotb[1] timeslotb[0] $09 devcfg6 $13 init2_ext async u_dir[1] u_dir[0] $12 u_rev[3] u_rev[2] u_rev[1] u_rev[0] $0a devcfg7 $15 month[3] month[2] month[1] month[0] $14 year[3] year[2] year[1] year[0] $0b devcfg8 $17 crc_u[2] crc_u[1] crc_u[0] day[4] $16 day[3] day[2] day[1] day[0] $0c sc $19 0 tm_b reserved iden_b $18 oc_init_b idef_b off_b tempf_b r bit range content sn[12:0] serial number sn[31:13] lot number
sensors freescale semiconductor, inc. 13 mma51xxkw 3.1.2 factory configuration register (devcfg1) the factory configuration register is a fact ory programmed, read only register which contains user specific device configuratio n information. the factory configuration register is in cluded in the factory programmed otp crc verification. 3.1.2.1 range indication bits (rng[2:0]) the range indication bits are factory programmed and indicate the full-scale range of the device as shown below. 3.1.3 device configuration 2 register (devcfg2) device configuration register 2 is a user programmable ot p register that contains dev ice configuration information. 3.1.3.1 user configuration lock bit (lock_u) the lock_u bit allows the user to prevent writes to the user configuration array once programming is completed. if the lock_u bit is written to ?1? when a psi5 ?execute pr ogramming of nvm? command is executed, the lock_u otp bit will be programmed. upon completion of the otp programming, an otp readout will be executed, locking the array from future otp writes. the user programmable otp array crc verification is also activated (reference section 3.2.2 ). 3.1.3.2 pcm enable bit (pcm) the pcm bit enables the pcm output pin. when the pcm bit is set, the pcm output pin is active and outputs a pulse code modulated signal proportional to the acceleration response. reference section 3.5.3.7 for more information regarding the pcm output. when the pcm bit is cleared, th e pcm output pin is actively pulled low. location bit a d d r e s sr e g i s t e r76543210 $ 0 4d e v c f g 100101r n g [ 2 ]r n g [ 1 ]r n g [ 0 ] f a c t o r y d e f a u l t00100000 rng[2] rng[1] rng[0] full-scale acceleration range g-cell design psi5 init data transmission (d9) reference table 12 0 0 0 reserved n/a 0001 0 0 1 60g medium-g 0111 0 1 0 reserved n/a 0010 0 1 1 120g medium-g 1000 1 0 0 reserved n/a 0011 1 0 1 240g high-g 1001 1 1 0 reserved n/a 0100 1 1 1 480g high-g 1010 location bit address register 7 6 5 4 3 2 1 0 $05 devcfg2 lock_u pcm sync_pd latency datasize blanktime p_crc baud f a c t o r y d e f a u l t00000000 pcm pcm output 0 actively pulled low 1 pcm signal enabled
sensors 14 freescale semiconductor, inc. mma51xxkw 3.1.3.3 sync pulse pulldow n enable bit (sync_pd) the sync pulse pulldown enable bit selects if the sync pulse pulldown is enabled once a sync pulse is detected. reference section 4.2.1.2 for more information regarding the sync pulse pulldown. if daisy chain mode is enabled, the sync pulse pulldown is enabled as listed below: 3.1.3.4 latency selection bit (latency) the latency selection bit selects between one of two data latency methods to accommodate synchronized sampling or simul- taneous sampling. reference section 4.5 for more information regarding latency and data synchronization. 3.1.3.5 data size selection bit (datasize) the data size selection bit selects one of two data lengths for the psi5 response message as shown below. 3.1.3.6 psi5 sync pulse blanking time selection bit (blanktime) the psi5 sync pulse blanking time selection bit selects the timi ng for ignoring sync pulses afte r successful reception of a sync pulse. reference section 4.2.1.1 for details regarding sync pulse detection and blanking. 3.1.3.7 psi5 res ponse message error detect ion selection bit (p_crc) the psi5 response message error detection selection bit selects ei ther even parity, or a 3-bit crc for error detection of the psi5 response message. reference section 4.3.3 for details regarding response message error detection. note: the psi5 specification recommends parity for data lengths of 10 bits or less. sync_pd sync pulse pulldown 0 disabled 1 enabled sync_pd daisy chain address programmed ?run mode? command received daisy chain address = ?001? sync pulse pulldown 0 x x x disabled 1 no x x enabled 1 yes no x disabled 1 yes yes no disabled 1 yes yes yes enabled latency data latency 0 simultaneous sampling mode (latency relative to sync pulse) 1 synchronous sampling mode (latency relative to time slot) datasize data length 0 10 bits 1 8 bits blanktime blanking time method 0 maximum of t sync_off_500 or response transmission complete 1 blanking time determined by end of res ponse transmission for programmed time slot p_crc parity or crc 0p a r i t y 1c r c
sensors freescale semiconductor, inc. 15 mma51xxkw 3.1.3.8 baud rate selection bit (baud) the baud rate selection bit selects one of two psi5 baud rates as shown below. reference section 2.6 for baud rate timing specifications. 3.1.4 device configuration registers (devcfg3, devcfg4, devcfg5) device configuration registers 3, 4, and 5 are user programmable otp regist ers which contain device configuration information. 3.1.4.1 psi5 transmission mode selection bits (trans_md[1:0]) the psi5 transmission mode selection bits select the psi5 transmission mode as shown below. 3.1.4.2 low-pass filter selection bit (lpf[1:0]) the low-pass filter selecti on bits select the low-pass filter for t he acceleration signal as described below: 3.1.4.3 timeslot selection bits (timeslotx[9:0]) the timeslot selection bits select the time slot(s) to be used for data transmission. reference section 4.5 for details regarding psi5 transmission modes and time slots. accepted time slot values are 0.5 s to 511.5 s in 0.5 s increments. care must be taken to prevent from programming time slots which violate the psi5 version 1.3 specification, or time slots which will cause d ata contention. note: timeslotb is only used for synchronous double sample rate mode and 16-bit resolution mode. baud baud rate 0 low baud rate (125 kbaud) 1 high baud rate (190.5 kbaud) location bit a d d r e s s r e g i s t e r76543210 $06 devcfg3 trans_md[1] trans_md[0] lpf[1] lpf[0] ti meslotb[9] timeslotb[8] timeslota[9] timeslota[8] $07 devcfg4 timeslota[7] timeslota[6] timeslota[5] timeslot a[4] timeslota[3] timeslota[2] timeslota[1] timeslota[0] $08 devcfg5 timeslotb[7] timeslotb[6] timeslotb[5] timeslot b[4] timeslotb[3] timeslotb[2] timeslotb[1] timeslotb[0] f a c t o r y d e f a u l t00000000 trans_md[1] trans_md[0] operating mode reference 0 0 normal mode (asynchronous or parallel, synchronous) section 4.5.1 0 1 synchronous double sample rate mode section 4.5.2 1 0 16-bit resolution mode (two 10-bit responses) section 4.5.3 1 1 daisy chain mode section 4.5.4 lpf[1] lpf[0] low-pass filter selected 0 0 400 hz, 3-pole 0 1 400 hz, 4-pole 10 r e s e r v e d 11 r e s e r v e d timeslotx[9:0] async bit time slot reference 00 0000 0000 0 default time slot (t timeslot_dflt ) from start of sync pulse (t trig ) section 4.5 1 asynchronous mode section 4.5.1.1 non-zero n/a timeslot definition from start of sync pulse (t trig ) in 0.5 s increments section 4.5
sensors 16 freescale semiconductor, inc. mma51xxkw 3.1.5 device configuration registers 6, 7, and 8 (devcfg6, devcfg7, devcfg8) device configuration registers 6, 7 and 8 are user programmable otp registers whic h contain device configuration and user specific manufacturing information. the user specific manufacturing information bits have no impact on the performance, but are transmitted during the psi5 initialization phase 2 in 10-bit mode. 3.1.5.1 initialization phase 2 da ta extension bit (init2_ext) the initialization phase 2 data extension bit enables or disables data transmission in data fields d27 through d32 of psi5 ini- tialization phase 2 as shown below. 3.1.5.2 asynchronous mode bit (async) the asynchronous mode bit enables asynchronous data transmission as described in section 3.1.4.3 . 3.1.5.3 user sensing di rection (u_dir[1:0]) the user sensing direction registers are user programmable ot p registers which contain the module level sensing direction. this data is transmitted to the main ecu during psi5 initialization phase 2 in 10-bit mode, as described in section 4.4.2.1 . 3.1.5.4 user product revision (u_rev[3:0]) the user product revision registers are user programmable otp registers which c ontain the module production revision. the device supports up to 16 product revisions. this data is transm itted to the main ecu during psi5 initialization phase 2 in 10-b it mode, as described in section 4.4.2.1 . location bit a d d r e s sr e g i s t e r76543210 $09 devcfg6 init2_ext async u_dir[1] u_dir[0] u_rev[3] u_rev[2] u_rev[1] u_rev[0] $0a devcfg7 month[3] month[2] month[1] m onth[0] year[3] year[2] year[1] year[0] $0b devcfg8 crc_u[2] crc_u[1] crc_u[0] d ay[4] day[3] day[ 2] day[1] day[0] f a c t o r y d e f a u l t 00000000 init2_ext description 0 d27 through d32 are set to ?0000? 1 d27 through d32 are transmitted as defined in section 4.4.2.1 u_dir[1] u_dir[0] module sensing direction as defined in aklv27 psi5 init data transmission (d8) reference table 12 0 0 connector direction ( ) 0000 0 1 bushing direction ( ) 0100 1 0 perpendicular to and () 1000 1 1 not used 1100
sensors freescale semiconductor, inc. 17 mma51xxkw 3.1.5.5 user production date information (year[3:0], month[3:0], day[4:0) the user production date information r egisters are user programmable otp regi sters which contain the module production date. the table below shows the relationship between the stored values and the production date. the julian date value is transmitted to the main ecu during psi5 initialization phase 2 in 10-bit mode, as described in section 4.4.2.1 . 3.1.5.6 user configuration crc (crc_u[2:0]) the user configuration crc bits contain the 3-bit crc used for verification of the user programmable otp array. reference section 3.2.2 for information regarding the crc for the user programmable otp array. programmed value decoded value julian date value year[3:0] year jy[6:0] 0000 2009 0001001 ? ? ? ? ? ? ? ? ? 1111 2024 0011000 month[3:0] month jm[3:0] 0000 n/a 0000 0001 january 0001 ? ? ? ? ? ? ? ? ? 1100 december 1100 ? ? ? ? ? ? ? ? ? 1111 n/a n/a day[4:0] day jd[4:0] 00000 n/a 00000 00001 day 1 00001 ? ? ? ? ? ? ? ? ? 11111 day 31 11111
sensors 18 freescale semiconductor, inc. mma51xxkw 3.1.6 status check register (sc) the status check register is a read-only register containing device status information. 3.1.6.1 test mode flag (tm_b) the test mode bit is cleared if the device is in test mode. 3.1.6.2 internal data error flag (iden_b) the internal data error bit is cleared if a register data crc f ault is detected in the user accessible otp array. a device rese t is required to clear the error. 3.1.6.3 offset cancellation in it status flag (oc_init_b) the offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and t he filter has switched to normal mode. 3.1.6.4 internal factory data error flag (idef_b) the internal factory data error bit is cleared if a register data crc fault is detect ed in the factory programmable otp array. a device reset is require d to clear the error. 3.1.6.5 offset error flag (off_b) the offset error flag is cleared if the a cceleration signal reaches the offset limit. 3.1.6.6 temperature error flag (tempf_b) the temperature error flag is cleared if an over or under temperature condition exists. location bit a d d r e s sr e g i s t e r76543210 $0c sc 0 tm_b reserved iden_b oc_init_b idef_b off_b tempf_b tm_b operating mode 0 test mode is active 1 test mode is not active iden_b error condition 0 crc error in user programmable otp array 1 no error detected oc_init_b error condition 0 offset cancellation in initialization 1 offset cancellation initialization complete (t oc1 and t oc2 expired) idef_b error condition 0 crc error in factory programmable otp array 1 no error detected off_b error condition 0 offset error detected 1 no error detected tempf_b error condition 0 over- or under-temperature error condition detected 1 no error detected
sensors freescale semiconductor, inc. 19 mma51xxkw 3.2 otp array crc verification 3.2.1 factory programmed ot p array crc verification the factory programmed otp array is verified for errors with a 3-bit crc. the crc verification is enabled only when the factory programmed array is locked. the crc verifica tion uses a generator polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. once the crc verification is enabled, the crc is continuously calc ulated on all bits in register s $00, $01, $02, $03, and $04 and on the factory programmable device config uration bits with the exception of the fact ory lock bit. bits are fed in from righ t to left (lsb first), and top to bottom (lower addresses first) in the register map. the calculat ed crc is then compared against th e stored 3 bit crc. if a crc error is detected in the otp array, the idef_b bit is cleared in the sc register. the crc verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array val- ues. 3.2.2 user programmable otp array crc verification the user programmable otp array is independently verified for errors with a 3-bit crc. the crc verification is enabled only when the lock_u bit in the user data register array is set afte r por, or after a psi5 programming mode ?execute programming of nvm? command. the crc verification us es a generator polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. the calcu- lated crc is compared against a user progr ammable 3-bit crc, crc_u[2:0], which is al so included in the user programmable array. once the crc verification is enabled, the crc is continuously calculated on all bits in registers $05, $06, $07, $08, $09, $0a, and $0b with the exception of the lock_u bit and the crc_u[2:0] bits. bits are f ed in from right to left (lsb first), and top t o bottom (lower addresses first) in the register map. the ca lculated crc is then compared again st the crc_u[2:0] bits. if a crc mismatch is detected, the iden_b bi t is cleared in the sc register. the crc verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array val- ues.
sensors 20 freescale semiconductor, inc. mma51xxkw 3.3 voltage regulators the device derives its internal supply voltage from the v cc and v ss pins. separate internal voltage regulators are used for the analog (v rega ) and digital circuitry (v reg ). the analog and digital regulators are supplied by a buffer regulator (v buf ) to provide immunity from emc and supply dropouts on v cc . external filter capacitors are required, as shown in figure 1 . the voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the internal voltages have increased above the under-voltage detecti on thresholds. the voltage monitor asserts internal reset when the external supply or internally regulated voltages fall below the under-voltage detection thresholds. a reference generator p ro- vides a reference voltage for the ? converter. figure 8. voltage regulation and monitoring v rega v reg v cc voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array oscillator ? converter bias generator trim trim v ref v ref_mod = 1.250 v v reg = 2.50 v voltage regulator v buf bandgap reference v buf v buf v ref v rega v ref por v cc comparator v ref comparator comparator v buf comparator v rega v reg voltage regulator micro-cut trim trim
sensors freescale semiconductor, inc. 21 mma51xxkw 3.3.1 v buf , v reg , and v rega regulator capacitor the internal regulators require an external capacitor between each of the regulator pins (v buf , v reg , or v rega ) and the as- sociated the v ss / v ssa pin for stability. figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 v cc , v buf , v reg , and v rega under-voltage monitor a circuit is incorporated to monitor the supply voltage (v cc ) and all internally regulated voltages (v buf , v reg , and v rega ). if any of internal regulator voltages fall below the specified under-voltage thresholds in section 2 , the device will be reset. if v cc falls below the specified threshold, psi5 transmissions are te rminated for the present response. once the supply returns above the threshold, the device will respond to the next detected sync pulse. reference figure 9 . figure 9. v cc micro-cut response v cc por v reg time v buf v rega v cc under-voltage detected response terminated i data v cc micro-cut occurs
sensors 22 freescale semiconductor, inc. mma51xxkw 3.3.3 v buf , v reg , and v rega capacitance monitor a monitor circuit is incorporated to ensure predicta ble operation if the connection to the external v buf , v reg , or v rega , ca- pacitor becomes open. in asynchronous mode, the v buf regulator is disabled t captest_adly seconds after each data transmission for a duration of t captest_time seconds. if the external capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset. in synchronous mode, the v buf regulator is disabled t captest_sdly seconds after each sync pulse for a duration of t captest_time seconds. if the external capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset. the v reg and v rega regulators are disabled at a continuous rate (t captest_rate ), for a duration of t captest_time seconds. if either external capacitor is not present, the associated regul ator voltage will fall below the internal reset threshold, for cing a device reset. figure 10. v buf capacitor monitor - asynchronous mode figure 11. v buf capacitor monitor - synchronous mode cap_test v buf time capacitor present v buf_uv_f por capacitor open t captest_time i data t captest_adly cap_test v buf time capacitor present v buf_uv_f por capacitor open t captest_time v cc t captest_sdly t trig
sensors freescale semiconductor, inc. 23 mma51xxkw figure 12. v reg capacitor monitor figure 13. v rega capacitor monitor 3.4 internal oscillator a factory trimmed oscillator is included as specified in section 2 . cap_test v reg time capacitor present por capacitor open t captest_time t captest_rate v porvreg_f cap_test v rega time capacitor present v porrega_f por capacitor open t captest_time t captest_rate
sensors 24 freescale semiconductor, inc. mma51xxkw 3.5 acceleration signal path 3.5.1 transducer the transducer is an overdamped mass-spring-damper sy stem defined by the following transfer function: where: = damping ratio n = natural frequency = 2 ? ? f n reference section 2.7 for transducer parameters. 3.5.2 ? converter a sigma delta modulator converts the differential capacitance of th e transducer to a 1 mhz data str eam that is input to the dsp block. figure 14. ? converter block diagram 3.5.3 digital signal processing block a digital signal processing (dsp) block is used to perform sign al filtering and compensation. a diagram illustrating the signal processing flow within the dsp block is shown in figure 15 . figure 15. signal chain diagram hs () n 2 s 2 2 n s ?? ? n 2 ++ --------------------------------------------------------- = 1-bit quantizer z -1 1 - z -1 z -1 1 - z -1 first integrator second integrator 1 = 1 2 2 v x c int1 g-cell c bot c top c = c top - c bot ? _out v = 2 v ref adc dac v = c x v x / c int1 ? _out sinc filter low-pass filter output output compensation a b c d interpolation scaling f offset rate limiting offset cancellation downsampling low-pass filter e cancellation output g h
sensors freescale semiconductor, inc. 25 mma51xxkw 3.5.3.1 decimation sinc filter the serial data stream produced by the ? converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16. figure 16. sinc filter response, t s = 16 s table 3. signal chain characteristics description sample time ( s) data width (bits) over range (bits signal width (bits) signal noise (bits) signal margin (bits) typical block latency reference a sd 1 1 1 203/f osc section 3.5.2 b sinc filter 16 20 13 section 3.5.3.2 c low-pass filter 16 26 4 10 3 9 reference section 3.5.3.2 section 3.5.3.2 d compensation 16 26 4 10 3 9 68/f osc e down sampling 16 26 4 10 3 9 f high pass filter 16 26 4 10 3 9 reference section 3.5.3.3 section 3.5.3.3 g dsp sampling 16 10 4/f osc section 3.5.3.5 10-bit output scaling h interpolation 1 10 64/f osc section 3.5.3.5 hz () 1z 16 ? ? 16 1 z 1 ? ? () ------------------------------------ - 3 =
sensors 26 freescale semiconductor, inc. mma51xxkw 3.5.3.2 low-pass filter data from the sinc filter is processed by an infinite impulse response (iir) low-pass filter. the device provides the option for one of two low-pass filters. the filter is selected with the lpf[1:0] bits in the devcfg3 register. the filter selection options are listed in section 3.1.4.2 . response parameters for the lo w-pass filter are specified in sec- tion 2.7 . filter characteristics are illustrated in figure 17 and figure 18 . note: low-pass filter values do not include g-cell frequency response. hz () a 0 n 11 z 0 ? () n 12 z 1 ? ? () n 13 z 2 ? ? () ++ d 11 z 0 ? () d 12 z 1 ? ? () d 13 z 2 ? ? () ++ ------------------------------------------------------------------------------------------------- n 21 z 0 ? () n 22 z 1 ? ? () n 23 z 2 ? ? () ++ d 11 z 0 ? () d 22 z 1 ? ? () d 23 z 2 ? ? () ++ ------------------------------------------------------------------------------------------------- ?? = table 4. low-pass filter coefficients description filter coefficients group delay 400 hz, 3-pole lpf a 0 5.189235225042199e-02 2816/f osc n 11 1.629077582099646e-03 d 11 1.0 n 12 1.630351547919014e-03 d 12 -9.481076477495780e-01 n 13 0d 13 0 n 21 2.500977520825902e-01 d 21 1.0 n 22 4.999999235890745e-01 d 22 -1.915847097557409e+00 n 23 2.499023243303036e-01 d 23 9.191065266874253e-01 400 hz, 4-pole lpf a 0 3.143225986084408e-03 3392/f osc n 11 9.951105668343345e-04 d 11 1.0 n 12 2.003487780064749e-03 d 12 -1.892328151433503e+00 n 13 1.008466113720278e-03 d 13 8.954713774195870e-01 n 21 2.516720624825626e-01 d 21 1.0 n 22 4.999888752940916e-01 d 22 -1.918978239761011e+00 n 23 2.483390622233452e-01 d 23 9.229853042218408e-01
sensors freescale semiconductor, inc. 27 mma51xxkw figure 17. low-pass filter characteristics: f c = 400 hz, 4-pole, t s = 16 s
sensors 28 freescale semiconductor, inc. mma51xxkw figure 18. low-pass filter characteristics: f c = 400 hz, 3-pole, t s = 16 s
sensors freescale semiconductor, inc. 29 mma51xxkw 3.5.3.3 offset cancellation the device provides an optional offset cance llation circuit to remove internal offset error. a block diagram of the offset canc el- lation is shown in figure 19 . figure 19. offset cancellation block diagram the transfer function for the offset lpf is: response parameters are specified in section 2 and the offset lpf coefficients are specified in table 6 . during startup, two phases of the offset lpf are used to allow fo r fast convergence of the internal offset error during initial iza- tion. the timing and characteristics of each phase are shown in table 5 and table 6 and specified in section 2 . for more infor- mation regarding the startup timing, referenc e the psi5 initialization information in section 4.4 . the offset low-pass filter used in normal operation is selected by the oc_filt bit as shown in table 5 . during the initialization self-test phase, the offs et cancellation circuit output value is frozen. during normal operation, output rate limiting is applied to th e output of the high pass filter. rate limiting updates the offse t cancellation output by off step_xx lsb every t offrate_xx seconds. to_output scaling offset cancellation a 0 n 1 n 2 z 1? ? () + d 1 d 2 z 1? ? () + ------------------------------------ - ? low-pass filter input data inc/dec counter clk out 0.5 hz (derived from f osc ) offmon neg offmon pos off_err inc/dec counter clk out up/down 2 khz (derived from f osc ) offmon cntlimit input data downsampled to 256 s hz () ao 0 no 1 no 2 z 1 ? ? () + do 1 do 2 z 1 ? ? () + ---------------------------------------------- ? = table 5. offset cancellation st artup characteristics and timing offset cancellation startup phase offset lpf output rate limiting total time for phase 1 10 hz bypassed 80 ms 2 0.3 hz bypassed 70 ms self-test 0.3 hz bypassed (frozen during st2) 96 ms per self-test sequence (up to 6 repeats) complete 0.1 hz enabled n/a
sensors 30 freescale semiconductor, inc. mma51xxkw figure 20. 10 hz offset cancellati on low-pass filter characteristics figure 21. 0.1 hz offset cancellation low-pass filter characteristics table 6. high pass filter coefficients description coefficients group delay 10 hz hpf ao 0 0.015956938266754 16.384 ms no 1 0.499998132328277 do 1 1.0 no 2 0.499998132328277 do 2 -0.984043061733246 0.3 hz hpf ao 0 0.000482380390167 537.6 ms no 1 0.499938218213271 do 1 1.0 no 2 0.499938218213271 do 2 -0.999517619609833 0.1 hz hpf ao 0 0.0001608133316040 1591ms no 1 0.4999999403953552 do 1 1.0 no 2 0.4999999403953552 do 2 -0.9998391270637512 0.04 hz hpf ao 0 0.0000643134117126 3976ms no 1 0.4999999403953552 do 1 1.0 no 2 0.4999999403953552 do 2 -0.9999356269836426
sensors freescale semiconductor, inc. 31 mma51xxkw 3.5.3.4 offset monitor the device includes an offset monitor circui t. the output of the single pole low-pass filter in the offset cancellation block i s continuously monitored against the offset limits specified in section 2.4 . an up/down counter is employed to count up if the output exceeds the limits, and to count down if the output is within th e limits. the output of the coun ter is compared against the cou nt limit offmon cntlimit . if the counter exceeds the limit, the off_b flag in the sc register is cleared. the counter rails once the max counter value is reached (offmon cntsize ). the offset monitor is disabled duri ng initialization phas e 1, phase 2, and phase 3. 3.5.3.5 data interpolation the device includes 16 to 1 linear data interpolation to minimize the system sample jitter. each result produced by the digital signal processing chain is delayed one sample time. on detection of a sync pulse the transmitted da ta is interpolated from the 2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of 1/1 6 of a sample time. reference section 4.5 for more information regarding interpolation and data latency. 3.5.3.6 output scaling the 26 bit digital output from the dsp is clipped and scaled to a 10-bit or 8-bit word which spans the acceleration range of th e device. figure 22 shows the method used to establ ish the output acceleration data word from the 26-bit dsp output. figure 22. 10-bit output scaling diagram 3.5.3.7 pcm output function the device provides the option for a pcm outp ut function. the pcm output is activate d if the pcm bit is set in the devcfg2 register. when the pcm function is enabled, a 4 mhz pulse code modulated signal proportional to the upper 9 bits of the 10-bit acceleration response is output onto the pcm pi n. the pcm output is intended for test use only. figure 23. pcm output function block diagram over range signal noise margin d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 ... d2 d1 d0 8-bit data word d21 d20 d19 d18 d17 d16 d15 d14 using rounding 10-bit data word d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 using rounding output scaling d[21:13] a 9 bit adder pcm b carry sum f clk = 4 mhz sample updated every 16 s 9 9 9 d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q section 3.5.3.6
sensors 32 freescale semiconductor, inc. mma51xxkw 3.6 overload response 3.6.1 overload performance the device is designed to operate within a specified range. acce leration beyond that range (overload) impacts the output of the sensor. acceleration beyond the range of the device can gener ate a dc shift at the output of the device that is dependent upon the overload frequency and amplitude. the g-cell is overdamped, providing the optimal design for overload performance. however, the performance of the device during an overload c ondition is affected by many other parameters, including: ? g-cell damping ? non-linearity ? clipping limits ? symmetry figure 24 shows the g-cell, adc and output cli pping of the device over frequency. the relevant parameters are specified in section 2 . figure 24. output clipping vs. frequency 3.6.2 sigma delta modulator over range response over range conditions exist when the signal level is beyond t he full-scale range of the device but within the computational limits of the dsp. the ? converter can saturate at levels above those specified in section 2 (g adc_clip ). the dsp operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. 5khz f g-cell f lpf g adc_clip g g-cell_clip determined by g-cell 10khz g-cell rolloff acceleration (g) frequency (khz) lpf rolloff r e g i o n c l i p p e d b y g - c e l l r e g i o n c l i p p e d b y a d c r e g i o n o f s i g n a l d i s to r ti o n d u e to a s y m m e tr y a n d n o n - l i n e a r i ty region of no signal distortion beyond specification region of interest roll-off and adc clipping g range_norm determined by g-cell roll-off and full-scale range region clipped by output
sensors freescale semiconductor, inc. 33 mma51xxkw 4 psi5 layer and protocol 4.1 communication interface overview the communication interface between a master device and the mma51xx is established via a psi5 compatible 2-wire inter- face, with parallel or serial (daisy-chain) connections to the satellite modules. figure 25 shows one possible system configuration for multiple satellite modules in parallel. figure 25. psi5 satellite interface diagram 4.2 data transmission physical layer the device uses a two wire interface for both its power supply (v cc ), and data transmission. the psi5 master supplies a pre- regulated voltage. data transmissions and synchronization control from the psi5 master to the device are accomplished via mod- ulation of the supply voltage. data transmissions from the devi ce to the psi5 master are accomplished via modulation of the cur - rent on the power supply line. 4.2.1 synchronization pulse the psi5 master modulates the supply voltag e in the positive direction to provide syn chronization of the satellite sensor data. upon reception of a synchronization pulse, the device delays a spec ified period of time, called a time slot, before transmittin g acceleration data. for more details regarding time slots, refer to section 3.1.4 , and section 4.5 . figure 26. synchronous communication overview mma51xx v cc i data satellite module #1 v cc v ss v cc_out v ss_out master device satellite module #2 v cc v ss v cc_out v ss_out discrete components discrete components v ss v cc i data v ss mma51xx gnd v idle sync pulses v idle + v sync i idle i idle + i mod
sensors 34 freescale semiconductor, inc. mma51xxkw 4.2.1.1 synchronization pulse detection the synchronization (sync) pulse detection block generates a va lid synchronization pulse signal following the detection of an externally generated sync pulse. this signal resets the sync pulse time reference (t trig ), and initiates the ti mers associated with response messages. the supply voltage can vary throughout the specified range, so the external sync pu lses may have different absolute voltage levels. thus, the sync pulse detection threshold (v cc_sync ) is dependent not only on the sync pulse absolute voltage, but also on the supply voltage. figure 27 shows a block diagram of the sync pulse detection circuit. figure 27. synchronization pulse detection circuit the start of a sync pulse is detect ed when the comparator output is set (v sync exceeds v sync_ref ). the comparator output is input into a counter, and the counter is updated at a fixed frequency of f osc /2. at a fixed time after the initial sync pulse detection (t sync_lpf_rst_st ), the counter is compared against a limit (the minimum value of t sync ). if the counter is above the limit, a valid sync pulse is detected. if the sync pulse is valid, the following occur: 1. the valid sync pulse detection signal is set. 2. the detection counter is reset and disabled for t sync_off (referenced from t trig ). t sync_off is a user programmable option. reference section 3.1.3.6 for details on the selectable option, and section 2.6 for timing specifications for each option. a. if blanktime = ?0?, t sync_off = t sync_off_500 a. if blanktime = ?1?, t sync_off =t sync_off_var = t timeslot_dlyx + (2+datasize+(p_crc?3:1)) *t bit_x 3. the sync pulse detection low-pass filter is reset for a specified time (t sync_lpf_reset). if the sync pulse is invalid, all timers are reset, a nd the detector becomes sensitive for the very next f sync_det sample. the output of the comparat or is monitored at the f osc /2 frequency. once the comparator out put goes high, all of the internal timers are started, so that the t trig jitter is minimized. f osc /2 sync_off v cc sync_lpf_reset v ss sync_det sync_offset sync_lpf d r counter control logic sync_lpf_reset v sync_ref v sync_comp
sensors freescale semiconductor, inc. 35 mma51xxkw figure 28. synchronization pulse detection timing 4.2.1.2 synchronization pulse pulldown function the device includes an op tional sync pulse pull down function for systems in which th e master device d oes not include an active pulldown function. the modulation current pulldown circuit is used, which sinks i mod -i idle additional current from the i data pin. the pulldown current is activated after t pd_dly (referenced to t trig ), and is activated for t pd_on . 4.3 data transmission data link layer 4.3.1 bit encoding the device outputs data by modulation of the v cc current using manchester 2 encoding. data is stored in a transition occurring in the middle of the bit time. the signal idles at the normal quiescent supply current. a logic low is defined as an increase i n current at the middle of a bit time. a logic high is defined as a decrease in current at the middle of a bit time. there is alw ays a transition in the middle of the bit time. if consecutive ?1? or ?0? data are transmit ted, there will also be a transition at th e start of a bit time. figure 29. manchester 2 data bit encoding sync pulse sync_lpf_reset sync off response t trig t sync_lpf_rst_st t timeslotx t sync_lpf_rst t sync_off_xxx v sync_comp t a_sync_dly sync_pulse_pd t pd_dly t pd_on i mod current ?0? bit consecutive ?0? data bits idle current ?1? bit sensed high t bit sensed low consecutive ?1? data bits
sensors 36 freescale semiconductor, inc. mma51xxkw 4.3.2 data transmission transmission frames are composed of two start bits, an 8-bit or 10-bit data word, and error detection bit(s). data words are transmitted least-significant bit (lsb) first. a typical manchester-encoded transmission frame is illustrated in figure 30 . figure 30. example manchester encoded data transfer - psi5-x10p 4.3.3 error detection error detection of the transmitted data is accomplished via either a parity bit, or a 3-bit crc. the type of error detection us ed is selected by the p_crc bit in the devcfg register. 4.3.4 parity error detection when parity error detection is selected, ev en parity is employed. the number of logic ?1? bits in the transmitted message must be an even number. 4.3.5 3-bit crc error detection when crc error detection is selected, a 3-bit crc is appende d to each response message. t he 3-bit crc uses a generator polynomial of g(x) = x 3 +x+1, with a seed value = ?111?. data from the tran smitted message is read in to the crc calculator lsb first, and the data is augmented with three ?0?s. start bits are not used in the crc calculation. table 7 shows some example crc calculation values for 10-bit data transmissions. table 7. psi5 3-bit crc calculation examples data transmitted crc hex d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c2 c1 c0 0x000 0 0 0 0 0 0 0 0 0 0 1 1 0 0x0cc 0 0 1 1 0 0 1 1 0 0 0 1 1 0x151 0 1 0 1 0 1 0 0 0 1 0 0 0 0x1e0 0 1 1 1 1 0 0 0 0 0 0 1 1 0x1f4 0 1 1 1 1 1 0 1 0 0 0 1 0 0x220 1 0 0 0 1 0 0 0 0 0 1 0 0 0x275 1 0 0 1 1 1 0 1 0 1 1 1 1 0x333 1 1 0 0 1 1 0 0 1 1 0 0 1 0x3ff 1 1 1 1 1 1 1 1 1 1 1 0 0 sb1 sb0 d0 d1 d2 d3 d4 d5 d8 d9 par ?0? ?0? ?1? ?1? ?1? ?0? ?0? ?1? ?1? ?0? ?1? data bit bit value d6 d7 ?1? ?1? t frame t bit t tran = t bit * (2+datasize+(p_crc?3:1)) i mod sb1
sensors freescale semiconductor, inc. 37 mma51xxkw 4.3.6 data range values ta b l e 9 shows the details for each data range. table 8. psi5 data values 8-bit data value 10-bit data value description decimal hex decimal hex +127 $7f +511 $1ff reserved ? ? ? ? ? ? +502 $1f6 +126 $7e +501 $1f5 +125 $7d +500 $1f4 sensor defect error message n/a n/a +499 $1f3 reserved ? ? ? ? ? ? +489 $1e9 +124 $7c +488 $1e8 sensor busy +123 $7b +487 $1e7 sensor ready +122 $7a +486 $1e6 sensor ready, but unlocked n/a n/a +485 $1e5 reserved ? ? ? ? ? ? +121 $79 +481 $1e1 +120 $78 +480 $1e0 maximum positive acceleration value ? ? ? ? ? ? ? ? ? ? ? ? positive acceleration values +3 $03 +3 $03 +2 $02 +2 $02 +1 $01 +1 $01 00000 g l e v e l -1 $ff -1 $3ff negative acceleration values -2 $fe -2 $3fe -3 $fd -3 $3fd ? ? ? ? ? ? ? ? ? ? ? ? -120 $88 -480 $220 maximum negative acceleration value -121 $87 -481 $21f initialization data codes 10-bit status data nibble 1 - 16 (0000 - 1111) (dx) 8-bit status data nibble 1 - 4 (00 - 11) (dx) ? ? ? ? ? ? ? ? ? ? ? ? -124 $84 -496 $210 -125 $83 -497 $20f initialization data ids block id 1 - 16 (10-bit mode) (idx) block id 1 - 4 (8-bit mode) (idx) ? ? ? ? ? ? ? ? ? ? ? ? -128 $80 -512 $200
sensors 38 freescale semiconductor, inc. mma51xxkw 4.4 initialization following powerup, the device proceeds through an initialization process which is divided into 3 phases: ? initialization phase 1: no data transmissions occur ? initialization phase 2: sensor self-test and transmission of configuration information ? initialization phase 3: transmi ssion of ?sensor busy?, and ?sensor ready? / ?sensor defect? message once initialization is completed the device begins normal mode operation, which continues as long as the supply voltage re- mains within the specified limits. figure 31. psi5 sensor 10-bit initialization during psi5 initialization, the device completes an intern al initialization process consisting of the following: ? power-on reset ? device initialization ? program mode entry verification ? offset cancellation initialization (2 stages) ?self-test figure 32 shows the timing for internal and external initialization. figure 32. initialization timing init 1 init 3 normal mode init 2 normal mode ... por gnd v idle v idle + v sync i idle i idle + i mod sync pulses ignored or program mode entry sync pulses t int_init t psi5_init1 self-test raw offset calculation psi5 initialization phase 1 t psi5_init2 t psi5_init3 psi5 initialization phase 2 psi5 initialization phase 3 psi5 normal mode por internal delay t oc1 offset cancellation stage 1 t st1 self-test deflection verification t st2 self-test normal data calculation t st3 st_rpt * t st self-test repeat (if necessary) t oc2 offset cancellation stage 2 programming mode entry 1) min. 31 sync pulses 2) pme command sync pulses ignored t rs_pm t pme no pm entry pm entry t prog_mode_start_delay no transmissions in response to sync pulses programming mode otherwise sync pulses ignored
sensors freescale semiconductor, inc. 39 mma51xxkw 4.4.1 psi5 initialization phase 1 during psi5 initialization phase 1, the device begins internal in itialization and self checks, but transmits no data. initializ ation begins with the sequence below and shown in figure 32 : ? internal delay to ensure analog circuitry has stabilized (t int_init ) ? offset cancellation phase 1 initialization (t oc1 ) ? monitor for the programming mode entry sequence (t pme ) ? a sequence of sync pulses received during the progr am mode entry window in psi5 initialization phase 1 will allow the device to enter into a psi5 programming mode if the lock_u bit is not set. reference section 5.2 for details. ? offset cancellation phase 2 initialization (t oc2 ) ? if the programming mode entry sequence is not dete cted, the device enters initialization phase 2 (t psi5_init2 ) 4.4.2 psi5 initialization phase 2 during psi5 initialization phase 2, the device contin ues it?s internal self checks and tr ansmits the psi5 in itialization phase 2 data. the psi5 initialization data transmission format varies depending on whether the device is programmed for 8-bit or 10-bit data. initialization is transmi tted using the initialization data codes and ids specified in table 12 , and in the order shown in figure 33 and figure 34 . figure 33. psi5 initialization phase 2 data transmission order (10-bit mode) figure 34. psi5 initialization phase 2 data transmission order (8-bit mode) the initialization phase 2 time is calculated with the following equation: where: ? trans nibble = # of transmissions per data nibble 2 for 10-bit data: 1 for id, and 1 for data 4 for 8-bit data: 2 for id, and 2 for data ? k = the repetition rate for the data fields ? data fields = 32 data fields for 10-bit data, 9 data fields for 8-bit data ?t s-s = sync pulse period d1 d2 ... d32 id1 1 d1 1 id1 2 d1 2 ... id1 k d1 k id2 1 d2 1 id2 2 d2 2 ... id2 k d2 k ... id32 1 d32 1 id32 2 d32 2 ... id32 k d32 k repeat k times repeat k times ... repeat k times d1 d2 ... d9 id1h 1 d1h 1 id1h 2 d1h 2 ... id1h k d1h k id1l 1 d1l 1 id1l 2 d1l 2 ... id1l k d1l k ... id9l 1 d9l 1 id9l 2 d9l 2 ... id9l k d9l k repeat k times repeat k times ... repeat k times t phase2 trans nibble k datafields () t ss ? =
sensors 40 freescale semiconductor, inc. mma51xxkw 4.4.2.1 psi5 initialization phase 2 (10-bit mode) in psi5 initialization phase 2, 10-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. the transmission data is in c onformance with the psi5 spec ification, revision 1.3 and aklv27, revision 1.10. the data content and transmission format is shown in table 9 and ta b l e 1 0 . table 9 shows the 10-bit phase 2 timing for different op- erating modes. times are calculated using the equation in section 4.4.2 . 1. offset and average self-test data will only be transmitted with sync pulse periods that guarantee the self-test phase1 and ph ase 2 will be complete prior to required transmission. if sync pulse periods faster than this are used, ?0?s will be transmitted instead of offset and/or avera ge self-test data. table 9. initialization phase 2 time (10-bit mode) operating mode repetition rate (k) # of transmissions nominal phase 2 time asynchronous mode (228 s) 8 512 116.7 ms synchronous mode (500 s) 4 256 128.0 ms table 10. psi5 initialization phase 2 data (10-bit mode) psi5 v1.2 field id # psi5 v1.2 nibble id # page address psi5 nibble address register address description value f1 d1 0 0000 hard-coded protocol revision = v1.3 0100 f2 d2, d3 0001, 0010 hard-coded number of data blocks = 32 0010 0000 f3 d4, d5 0011, 0100 hard-coded manufacturer = freescale 0100 0110 f4 d6, d7 0101, 0110 hard-coded sensor type = acceleration (high-g) 0000 0001 f5 d8 0111 u_dir[1:0] = 00: 0000 u_dir[1:0] = 01: 0100 u_dir[1:0] = 10: 1000 u_dir[1:0] = 11: 1100 (not used) axis user d9 1000 60g: 0111 120g: 1000 240g: 1001 480g: 1010 range varies f6 d10 1001 devcfg2[7:4] sensor specific information user d11 1010 devcfg2[3:0] sensor specific information user f7 d12 1011 hard-coded product revision 0001 d13 1100 hard-coded product revision 0001 d14 1101 devcfg6[3:0] product revision user f8 d15 1110 devcfg7[7:0], devcfg8[4:0] converted to binary coded julian date reference section 3.1.5.5 jy[6:3] user d16 1111 jy[2:0], jm[3] user d17 1 0000 jm[2:0], jd[1] user d18 0001 jd[3:0] user f9 d19 0010 sn0 (high nibble) mma51xx serial number factory d20 0011 sn0 (low nibble) mma51xx serial number factory d21 0100 sn1 (high nibble) mma51xx serial number factory d22 0101 sn1 (low nibble) mma51xx serial number factory d23 0110 sn2 (high nibble) mma51xx serial number factory d24 0111 sn2 (low nibble) mma51xx serial number factory d25 1000 sn3 (high nibble) mma51xx serial number factory d26 1001 sn3 (low nibble) mma51xx serial number factory d27 1010 initial raw offset (offset[3:0]) raw offset 1 (if init2_ext=1, ?0000? otherwise) varies d28 1011 initial raw offset (offset7:4]) raw offset 1 (if init2_ext=1, ?0000? otherwise) varies d29 1100 ([avgselftest[1:0],offset[9:8]]) raw off/avg st 1 (if init2_ext=1, ?0000? otherwise) varies d30 1101 average self-test (avgselftest[5:2]) avg self-test 1 (if init2_ext=1, ?0000? otherwise) varies d31 1110 average self-test (avgselftest[9:6]) avg self-test 1 (if init2_ext=1, ?0000? otherwise) varies d32 1111 devcfg1 [7:4] sensor specific (if init2_ext=1, ?0000? otherwise) 0010
sensors freescale semiconductor, inc. 41 mma51xxkw 4.4.2.2 initialization phase 2 (8-bit mode) in psi5 initialization phase 2, 8-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. the transmission data uses a format similar to the psi 5 specification, revision 1.3 10-bit format modified for 8-b it transmission. the data content and transmission format is shown in table 11 and table 12 . ta b l e 11 shows the 8-bit phase 2 timing for different operating modes. times are calculated using the equation in section 4.4.2 . table 11. initialization phase 2 time (8-bit mode) operating mode repetition rate (k) # of transmissions nominal phase 2 time asynchronous mode 0 (228 s) 16 576 131.3 ms synchronous mode (500 s) 8 288 144.0 ms table 12. psi5 initialization phase 2 data (8-bit mode) psi5 v1.2 field id # psi5 v1.2 nibble id # page address psi5 half-nibble address register address description value f1 d1 h 0 00 hard-coded protocol revision = v1.3 01 f1 d1 l 0 01 hard-coded protocol revision = v1.3 00 f2 d2 h 0 10 hard-coded number of data blocks = 9 00 f2 d2 l 0 11 hard-coded number of data blocks = 9 10 f2 d3 h 1 00 hard-coded number of data blocks = 9 00 f2 d3 l 1 01 hard-coded number of data blocks = 9 00 f3 d4 h 1 10 hard-coded satellite manufacturer = freescale 01 f3 d4 l 1 11 hard-coded satellite manufacturer = freescale 00 f3 d5 h 2 00 hard-coded satellite manufacturer = freescale 01 f3 d5 l 2 01 hard-coded satellite manufacturer = freescale 10 f4 d6 h 2 10 hard-coded sensor type = acceleration (high-g) 00 f4 d6 l 2 11 hard-coded sensor type = acceleration (high-g) 00 f4 d7 h 3 00 hard-coded sensor type = acceleration (high-g) 00 f4 d7 l 3 01 hard-coded sensor type = acceleration (high-g) 01 f5 d8 h 3 10 u_dir[1:0] = 00: 0000 u_dir[1:0] = 01: 0100 u_dir[1:0] = 10: 1000 u_dir[1:0] = 11: 1100 (not used) axis user f5 d8 l 3 11 user f5 d9 h 4 00 60g: 0111 120g: 1000 240g: 1001 480g: 1010 range varies f5 d9 l 4 01 varies
sensors 42 freescale semiconductor, inc. mma51xxkw 4.4.3 internal self-test during psi5 initialization phase 2 and phase 3, the device comp letes it?s internal self-test as described below and shown in figure 32 . ? self-test phase 1 - raw offset calculation ? the average offset is calculated for t st1 (self-test disabled). ? if the init2_ext bit is set, this 10-bit value is transmitted in initialization phase 2 (reference section 4.4.2 ). ? self-test phase 2 - self-test deflection verification ? the offset cancellation value is frozen for t st2 + 2ms ? self-test is enabled ?after t st2 /2, the acceleration output value is averaged for t st2 /2 to determine the self-test value ? if the init2_ext bit is set, this10-bit value is transmitted in initialization phase 2 (reference section 4.4.2 ). ? the self-test value is compared against the limits specified in section 2.5 ? self-test is disabled ? self-test phase 3 - self-test normal data calculation ? the average offset is calculated for t st3 ? if self-test passed, the device advances to normal mode ? if self-test failed, the device repeats self-t est phases 1 through 3 up to st_rpt times. 4.4.4 initialization phase 3 during psi5 initialization phase 3, the device completes it?s in ternal self checks, and transmit s a combination of ?sensor busy ?, ?sensor ready?, or ?sensor defect? messages as defined in table 8 . the number of messages transmitted in initialization phase 3 varies depending on the mode of operation, and the number of self-test repetitions. se lf-test is repeated on failure up to st_rpt times to provide immunity to misuse inputs during in itialization. self-test terminates successfully after one successful self-test sequence. ta b l e 1 3 shows the nominal initialization phase 3 times for differen t operating modes and self-tes t repeats. times are calcu- lated using the following equation. table 13. initialization phase 3 time operating mode self-test repetitions # of sensor busy messages # of sensor ready or sensor defect messages nominal phase 3 time (ms) 8-bit asynchronous mode 0 (228 s) 00 2 0.46 1 359 82.31 2 780 178.30 3 1201 274.28 4 1622 370.27 5 2043 466.26 10-bit asynchronous mode 0 (228 s) 02 0 . 9 1 1 423 96.90 2 844 192.89 3 1265 288.88 4 1686 384.86 5 2107 480.85 8-bit synchronous mode (500 s) 00 1 . 0 0 1 138 70.00 2 330 166.00 3 522 262.00 4 714 358.00 5 906 454.00 10-bit synchronous mode (500 s) 00 1 . 0 0 1 170 86.00 2 362 182.00 3 554 278.00 4 746 374.00 5 938 470.00 t psi5init3 roundup t intinit t oc1 t oc2 t st1 t st2 t st3 ++ () strpt 1 + () +++ () t psi5init1 t psi5init2xx + () ? t ss ? --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2 + ? ? ? ? t ss ? =
sensors freescale semiconductor, inc. 43 mma51xxkw 4.5 psi5 transmission modes 4.5.1 normal mode 4.5.1.1 asynchronous mode the device can be programmed to respond in asynchronous mode with the following settings: ? trans_md[1:0] = ?00? (?normal mode?) ? async = ?1? in the devcfg6 register ? timeslota[9:0] = 0x000 in the devcfg3 and devcfg4 registers in asynchronous mode, the device transmits data at a fixed rate (t async ) and will not respond to normal sync pulses. however, during initialization phase 1, sync pulses are monitored to decode the programming mode entry command and allow entry into programming mode if the lock_u bit is not set. 4.5.1.2 simultaneous sampling mode the device can be programmed to respond in simultaneous sampling mode by setting the trans_md[1:0] bits to ?normal mode?, and by programming the latency bit to ?simultaneous sampling mode?. in simultaneous sampling mode, the most recent interpolated acceleration data sample is latched at t trig (rising edge of sync pulse) and transmitted starting at the time programmed in timeslota[9:0], relative to t trig . figure 35. simultaneous sampling mode t lat_interp t timeslota
sensors 44 freescale semiconductor, inc. mma51xxkw 4.5.1.3 synchronous sampling mode with minimum latency the device can be programmed to respond in synchronous sampling mode with minimum latency by setting the trans_md[1:0] bits to ?normal mode?, and by programm ing the latency bit to ?synchronous sampling mode?. in synchronous sampling mode, the most rece nt interpolated acceleration data sample is latched at the time programmed in timeslota[9:0], relative to t trig (rising edge of sync pulse). the data is tran smitted starting at the time programmed in timeslota[9:0], relative to t trig . figure 36. synchronous sampling mode with minimum latency t timeslota t lat_interp + t datasetup_synch
sensors freescale semiconductor, inc. 45 mma51xxkw 4.5.2 synchronous double sample rate mode the device can be programmed to respond in synchronous d ouble sample rate mode with minimum latency by setting the trans_md[1:0] bits to ?synchronous double sample rate mode ?. the latency bit does not affect operation in this mode. in synchronous double sample rate mode, t he most recent interpolated acceleration data sample is latched at the time pro- grammed in timeslota[9:0], relative to t trig (rising edge of sync pulse). this data is transmitted starting at the time pro- grammed in timeslota[9:0], relative to t trig . in addition, the most recent interpolat ed acceleration data sample is latched at the time programmed in tim eslotb[9:0], relative to t trig (rising edge of sync pulse) this data is transmitted starting at the time programmed in timeslotb[9:0], relative to t trig . when synchronous double sample rate mode is enabled, psi5 in itialization data is transmitted in both timeslota[9:0] and timeslotb[9:0]. identical data is transmitted in both time slots, including the 10-bit resolution raw offset and self-test data in field 9, d27 though d31 if enabled. figure 37. synchronous double sample rate mode note: in the event that the prog rammed values in timeslota [9:0] and timeslotb [9:0] result in a conflict, no data will be transmitted in timeslotb [9:0] . t timeslota t lat_interp +t datasetup_double t lat_interp +t datasetup_double t timeslotb
sensors 46 freescale semiconductor, inc. mma51xxkw 4.5.3 16-bit resolution mode the device can be programmed to respond in 16-bit resolution mode by setting the trans_md[1:0] bits to ?16-bit resolution mode?. in this mode, the 26 bit digital output fr om the dsp is clipped and scaled to a 16-bit word. figure 38 shows the method used to establish the 16-bit data word from the 26 bit dsp output. figure 38. 16-bit output scaling diagram 16-bit resolution mode can be programm ed to operate in either ?simultaneous sampling mode?, or ?synchronous sampling mode?, by setting the latency bit to the desired operating mode. in simultaneous sampling mode, the most recent interpolated acceleration data sample is latched at t trig (rising edge of sync pulse). in synchrono us sampling mode, the most recent inter- polated acceleration data sample is latched at the time programmed in timeslota[9:0], relative to t trig (rising edge of sync pulse). the most significant 10 bits (d[21:12]) are truncated and transm itted starting at the time programmed in timeslota[9:0], rel- ative to t trig . the 16-bit value is then clipped to 480 counts, and the least significant 10 bits (d15:d6) are transmitted starting at the time programmed in timeslotb[9:0], relative to t trig . when 16-bit resolution mode is enabled, psi5 initializat ion data is transmitted in both timeslota[9:0] and timeslotb[9:0]. identical data is transmitted in both time slots, including the 10-bit resolution raw offset and self-test data in field 9, d27 though d31 if enabled. figure 39. 16-bit resolution mode with synchronous sampling note: in the event that the prog rammed values in timeslota [9:0] and timeslotb [9:0] result in a conflict, no data will be transmitted in timeslotb [9:0] . over range signal noise margin d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 ... d2 d1 d0 16-bit data word d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 using rounding t lat_interp + t datasetup_16 t timeslota t timeslotb
sensors freescale semiconductor, inc. 47 mma51xxkw 4.5.4 daisy chain mode the device can be programmed to operate in daisy chain mode by setting the trans_md[1:0] bits to ?daisy chain mode?. daisy chain mode can be programmed to operate in either ?s imultaneous sampling mode?, or ?synchronous sampling mode? by setting the latency bit to the desired operating mode. in si multaneous sampling mode, the most recent interpolated accel- eration data sample is latched at t trig (rising edge of sync pulse). in synchronous sampling mode, the most recent interpolated acceleration data sample is latched at the time programmed in timeslota[9:0], relative to t trig (rising edge of sync pulse). when programmed to operate in daisy chain mode, the procedure below is followed: ? on powerup, the device proceeds through no rmal psi5 initialization as specified in section 4.4 using a predefined time slot t timeslot_dcp . ? upon successful completion of initialization phase 3, including the 2 ?sensor ready? or sensor defect? messages, responses to sync. pulses are terminated and the device waits for a psi5 ?set address? command defined in ta b l e 1 4 and table 15 . ? the daisy chain programming command and response formats are defined in section 5.4 . ? valid daisy chain addresses are defined in ta b l e 1 6 . ? the response to the psi5 set address command uses the predefined time slot t timeslot_dcp . ? after receiving a valid address and completing the response, sync. pulses are blanked for t dc_blanking . once the blanking time expires, the device does not respond to any sync. pulses until a ?run mode? command is received, as defined in table 14 and ta b l e 1 5 . ? when the ?run mode? command is received, the device responds to this command using the programmed daisy chain time slot. all commands are then ignored, and sync pulses are responded to with acceleration data using the following response format, regardless of the state of the relevant bits in the device configuration registers: ? during initialization and run mode, the sync pulse pulldown is enabled as specified in section 3.1.3.3 . parameter reference value time slot section 3.1.4.3 default time slot specified in table 16 data size section 3.1.3.5 10-bit data error checking section 3.1.3.7 even parity baud rate section 3.1.3.8 low baud rate: 125 kbaud table 14. daisy chain programming commands and responses # cmd type sadr fc command response (ok) response (error) a2 a1 a0 f2 f1 f0 rc rd1 rc rd1 d0 short 0 0 0 a2 a1 a0 set sensor address (daisy chain) ok sadr error errn d1 short 1 1 1 0 0 0 broadcast message - ?run mode? ok 0x000 error errn table 15. daisy chain programming response code definitions response code definition value rc = ok command message received properly 0x1e1 rc = error error during transmission of command message 0x1e2 sadr programmed sensor address, prepended with 0s varies table 16. valid daisy chain addresses sensor address (sadr) description bus switch control default time slot a2 a1 a0 0 0 0 address of unprogrammed sensor n/a n/a 0 0 1 sensor address 1 closed t timeslot_dc1 0 1 0 sensor address 2 closed t timeslot_dc2 0 1 1 sensor address 3 closed t timeslot_dc3 1 0 0 sensor address 4 open t timeslot_dc1 1 0 1 sensor address 5 open t timeslot_dc2 1 1 0 sensor address 6 open t timeslot_dc3 1 1 1 global address for broadcast message to all sensors n/a n/a
sensors 48 freescale semiconductor, inc. mma51xxkw 4.6 error handling 4.6.1 sensor defect message the following failures will cause the device to transmit a ?sensor defect? error message: 4.6.2 no response error the following failures will cause the device to stop transmitting: error condition error type offset error temporary (normal transmissions continue once o ffset returns within limits) self-test failure latched until reset iden_b, idef_b flag cleared latched until reset error condition error type under-voltage failure (v cc ) temporary: normal transmi ssions continue once voltage returns above failure limit) under- / over-temperature failure temporary: normal transmissions cont inue once temperature returns within the specified limits )
sensors freescale semiconductor, inc. 49 mma51xxkw 5 programming mode via psi5 5.1 introduction programming mode via psi5 is a synchronous communication mo de that allows for bidirectional communication with the de- vice. programming mode is intended for factory programming of the otp array. it is not intended for use in normal operation. 5.2 programming mode via psi5 entry the device enters programming mode if a nd only if the following sequence occurs: ? the device is unlocked (the lock_u bit in the devcfg2 register is ?0?). ? at least 31 sync pulses are detected, directly preceding the programming mode entry short command during the programming mode entry window shown in figure 32 . ? the window timing is defined in section 2.6 (t pme ). ? the sync pulses and programming mode entry command must be received with a sync pulse period of t s-s_pm_l if the programming mode entry requirement is not met: ? programming mode entry is blocked until the device is reset. ? the device proceeds with psi5 initializa tion phase 2, and psi5 initialization phase 3. ? the device enters normal mode, and responds as programmed to normal sync pulses. if the programming mode entry requirement is met: ? normal transmissions to sync pulses are terminated. ? after a predefined start delay, the device begins to decode psi5 short and long commands. ? the device responds only to valid psi5 short and long commands addressed to sensor address ?001?, as defined in ta b l e 1 8 . note: the sync pulse pulldown is disabled in the programming mo de entry window regardless of the state of the syncpd bit.
sensors 50 freescale semiconductor, inc. mma51xxkw 5.3 programming mode via psi5 - data link layer 5.3.1 programming mode via psi5 - command bit encoding commands messages are transmitted via the modulation of the supply voltage. the pres ence of a sync pulse is a logic '1' and the absence of a sync pulse is a logic '0'. sync pulses are expected at a rate of t s-s_pm_l . 5.3.2 programming mode via psi5 - command message format command message data frames consist of a start condition, 3 st art bits (s[2:0]), a 3 bit sensor address (sadr[2:0]), a 3-bit function code (fc[2:0]), an optional register address (radr[5:0]), an optional data field (d[3:0]), and a 3-bit crc (c[2:0]. th e start condition consists of one of the following: 1. a minimum of 5 consecutive logic ?0?s (with not sync bits) 2. a minimum of 31 consecutive logic ?1?s the command message format is shown in figure 41 . figure 40. programming mode via psi5 command data format bit stuffing is necessary to maintain a synchronized time base between the command master and the device. a logic ?1? sync bit is added every 4 th bit in the command message to ensure there will never be more than 3 logic '0' bits in a row. figure 41. programming mode via psi5 command data format with sync bits once a command is received and verified, the device expec ts 2 to 3 consecutive sync pulses (depending upon the command message lengths described below). for each of these sync pulses, the device will respond with the following settings: figure 42. programming mode via psi5 response message settings start bits sensor address function code register address data crc response s2 s1 s0 sa0 sa1 sa2 fc0 fc1 fc2 ra0 ra1 ra2 ra3 ra4 ra5 d0 d1 d2 d3 c2 c1 c0 rc rd1 rd0 0101000100000001111000 $3ff$3ff$3ff crc data to be written to register (optional) register address (optional) function codes for mma51xx (reference section 5.3.6 ) sensor address - fixed at 001 for mma51xx start bit sequence = 010 start bits sensor address function code register address data crc response s2 s1 s0 sy sa0 sa1 sa2 sy fc0 fc1 fc2 sy ra0 ra1 ra2 sy ra3 ra4 ra5 sy d0 d1 d2 sy d3 c2 c1 sy c0 rc rd1 rd0 010 11 0 0 10 0 0 10 0 0 10 0 0 1111 1100 1 0 $1e2 $3ff $3ff parameter register bits reference value time slot n/a n/a t timeslot_dc1 data size datasize = 0 section 3.1.3.5 10-bit data error checking p_crc = 0 section 3.1.3.7 even parity baud rate baud section 3.1.3.8 125 kbaud sync pulse pulldown syncpd section 3.1.3.3 disabled
sensors freescale semiconductor, inc. 51 mma51xxkw 5.3.2.1 short frame command and response format short frames are the simplest type of co mmand message. no data is transmitted in a short frame command. only specific instructions are performed in response to short fr ame commands. the short frame format is shown in figure 43 . short frame commands and responses are defined in section 5.3.6 , table 18. figure 43. programming mode via psi5 short command and response format 5.3.2.2 long frame command and response format long frames allow for the transmission of data nibbles for regi ster writes. the device can provi de register data in response to a read or write request. the long frame format is shown in figure 44 . long frame commands and responses are defined in section 5.3.6 . figure 44. programming mode via psi5 long command and response format 5.3.3 command message crc programming mode command error checking is accomplished by a 3-bit crc. the 3-bit crc is calculated using all message bits except start bits and sync bits. the crc verification uses a generator polynomial of g(x) = x 3 +x+1, with a seed value = ?111?. the data is provided to the crc calculator in the order received (lsb first, sadr, fc, radr, data), and then augmented with thr ee ?0?s. table 8 shows some example crc calculation values for 10-bit data transmissions. the calculated crc is then compared against the received 3- bit crc (received msb first). if a crc mismatch is detected, the device responds with a crc error response as defined in section 5.3.7 . 5.3.4 command sync pulse blanking time in programming mode and programming mode entry, the device employs a fixed sync pulse blanking time of t sync_off_500 regardless of the state of the blanktime bit. 5.3.5 command timeout in the event that the device does not de tect a sync pulse within a 4-bit window time (missing sync bit), the command reception will be terminated and the device will respond to the next sync pulse with a short frame framing error response as defined in section 5.3.7 . start bits sensor address function code crc response s2 s1 s0 sy sa0 sa1 sa2 sy fc0 fc1 fc2 sy c2 c1 c0 rc rd1 010 11 0 0 10 0 1 1 0 0 0 $1e2 $3ff start bits sensor address function code register address data crc response s2 s1 s0 sy sa0 sa1 sa2 sy fc0 fc1 fc2 sy ra0 ra1 ra2 sy ra3 ra4 ra5 sy d0 d1 d2 sy d3 c2 c1 sy c0 rc rd1 rd0 010 1100 10 1 0 1000 10 0 0 1111 1100 1 0 $1e2 $3ff $3ff
sensors 52 freescale semiconductor, inc. mma51xxkw 5.3.6 programming mode via psi5 command and response summary note: when reading the last address in the data array, rdata+1 will always return 0x00. 5.3.7 programming mode via psi5 error response summary * errn is transmitted in the 4 lsbs of rd1. all other bits in the response data field are set to ?0?. table 17. programming mode via psi5 commands and responses # cmd type sadr fc command register address data field response (ok) response (error) rc rd1 rd0 rc rd1 rd0 s0 short 001 100 execute programming of nvm n/a n/a ok 0x2aa n/a error errn n/a s1 short 101 invalid command n/a n/a no response no response s2 short 110 invalid command n/a n/a no response no response s3 short 111 enter programming mode n/a n/a ok 0x0ca n/a no response lr long 010 read nibble located at address ra5:ra0 varies varies ok rdata rdata+1 error errn 0x000 lw long 011 write nibble to register ra5:ra0 varies varies ok wdata ra5:ra0 error errn 0x000 xlr xlong 000 invalid command any any no response no response xlw xlong 001 invalid command any any no response no response table 18. programming mode via psi5 response code definitions response code definition value rc = ok command message received properly 0x1e1 rc = error error during transmission of command message 0x1e2 rdata byte contents of register located at byte add ress in which nibble address ra5:ra0 falls in. (example: for ra5:ra0 = $04 - rdata = data at byte address $02) varies rdata + 1 byte contents of register located at byte addr ess in which nibble address ra5:ra0 +2 falls in. (example: for ra5:ra0 = $04 - rdata + 1= data at byte address $03) varies wdata byte contents of register located at byte address in which nibble address ra5:ra0 falls in after write operation. (example: for ra5:ra0 = $04 - rdata = data at byte address $02) varies table 19. error response summary errn* mnemonic description supported by mma51xx 0000 general general error no 0001 framing framing error yes 0010 crc crc error on received message yes 0011 address sensor address not supported no (invalid address is ignored) 0100 fc function code not supported no (n/a) 0101 data range unsupported register address yes 0110 write protect destination address is write protected (locked) yes 0111 reserved reserved no 1000 reserved reserved no 1001 1010 1011 1100 1101 1110 1111
sensors freescale semiconductor, inc. 53 mma51xxkw 5.4 otp programming via psi5 procedure 1. enter programming mode. 2. load desired data into the otp shado w registers using psi5 long write commands. 3. send ?execute programming of nvm ?short command. 4. set v cc = v pp prior to, or within t prog_hold after the ?execute programming of nvm? command has been transmitted. there is an internal delay of t prog_delay after the ?execute program ming of nv? command is received until the otp programming begins. a. otp write time depends on the number of bits be ing written to ?1?. each bit that is programmed requires t prog_bit . b. during the otp write sequence, sync pulses will be ignored. however, transmission of sync pulses during the otp write sequence should be prevented. 5. read the sc register and verify idef_b flag is set (ind icating the write is complete and successful, and the shadow registers have been refres hed with the otp contents). 6. read the otp register values and compare to the desired values.
sensors 54 freescale semiconductor, inc. mma51xxkw 6 package 6.1 case outline drawing reference freescale case outline drawing # 98asa00090d http://www.freescale.com/files/shared /doc/package_info/98asa00090d.pdf 6.2 recommended footprint reference freescale application note an3111, latest revision: http://www.freescale.com/files /sensors/doc/app _note/an3111.pdf table 20. revision history revision number revision date description of changes 9 03/2012 ? added safeassure logo, changed first paragraph and disclaimer to include trademark information. ? table 2: $04 devcfg1: changed bit function 3 to 1. ? section 3.1.2: changed bit 3 to 1 in register table. ? section 3.1.2.1: removed axis column in table, changed last row g-cell design column to high-g.
mma51xxkw rev. 9 03/2012 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses gr anted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserv es the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discla ims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does no t convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or aut horized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconducto r products for any such unintended or unauthorized application, buyer shall inde mnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and r easonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. safeassure and xtrinsic are trademarks of freescale semiconductor, inc. ? 2012 freescale semiconductor, inc. all rights reserved. rohs-compliant and/or pb-free versions of freesca le products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sale s representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp.

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